A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform

In this paper, an efficient VLSI architecture for a fast computation of the 2-D discrete wavelet transform (DWT) is proposed. The architecture employing a three-stage cascade in pipeline mode enhances the computing time by appropriately distributing the overall computational load among the three stages and by incorporating parallelism at various hierarchies of the architecture. The computing time is further enhanced by making use of a scheme for the equalization of the data paths in terms of the delays in the computational blocks of the architecture. A Verilog simulation of the proposed architecture is carried out to demonstrate the superior performance of the architecture.