A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider

In this paper, a novel architecture of a fractional-
N
phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ΔΣ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) ΔΣ fractional-
N
PLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.