A 3.7mW, 1.6V CMOS Analog Adaptive Equalizer for a 125Mbps Wire-Line Transceiver

An analog adaptive equalizer based on feed-forward architecture is implemented on 0.18μm digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125Mbps over UTP CAT-5 cable of up to 100m length. Novel low-voltage, low-power circuit techniques resulted in 3.7mW total power consumption and supply voltage operation as low as 1.6V. This is over 3times power savings and 0.4V reduction in supply voltage from previously reported implementations on the same process node. The minimum horizontal eye opening of the equalizer (including the transmit path driver) under all cable length is 0.67 UI and the total area of the equalizer is 27738
μ
m
²
.