Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

In this paper, the authors study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages. The authors show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. The authors propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25
μ
m, 0.18
μ
m and 0.13
μ
m CMOS).