New Encapsulation Process for the SIP (System in Package)

System-in-Package (SiP) is a promising concept of system integration. Different semiconductor technologies, integrated passives, and other components can be integrated into a single package, without compromising the performance of separate functional blocks. However, the increase of packaging density increases the complexity of structures. Therefore, new processes and materials are needed to achieve high reliable SiP module pkg. So in this test, we tried VPES (vacuum printing encapsulation system) as underfill and encapsulation process of SiP module. The size of SiP module package is 4.84(L) times 6.15(W) times 1.32(H) mm. It contains an IC chip and several passive components such as crystals, filters, register, capacitor, etc. IC chip size is 3.5 mm SQ, thickness 0.45 mm, and the standoff height is almost 0.06 mm. In this test we compared VPES and conventional underfill and molding process. During the VPES process we used pressure cure system to reduce the internal void size. SAT (scanning acoustic transmitter), 3D optical microscope, and shadow moire analysis were done. And reliability test such as MRT and T/C was performed.