Coding for Minimizing Energy in VLSI Interconnects

In CMOS VLSI circuits, the dynamic power dissipation contributes a significant fraction in the overall power dissipation. Hence, the main target of VLSI designers is to minimize the switching activity on the on-chip bus lines. In this paper, the authors propose a novel bus encoding technique which minimizes both self and coupling transition activity to curtail the global power dissipation. The performance of the proposed coding scheme has been tested on various SPEC'95 benchmarks and found that with respect to unencoded data, an average reduction of 28% and 26% with respect to self and coupling energies in the total power dissipation is achieved. The hardware, used for encoding and decoding purposes, has been designed using Magma©tools.