Reconfigurable Low Power FIR Filter based on Partitioned Multipliers

This paper presents a low power programmable FIR filter based on partitioned multipliers. Architecture chosen for implementation is conventional direct form. Power efficient techniques like unsigned multiplication and reduction of switching activity are used. Paper presents power, area and speed analysis of the proposed design. FIR Filter is fully parameterized, dynamically programmable and technology independent. Results are presented for 20-tap FIR filter implemented on Xilinx Vertex-II FPGA 2s200fg256-6. Maximum power saving of 48.2% is achieved with an area overhead of 2.08 % only.