High Performance and High Reliability Dual Metal CMOS Gate Stacks Using Novel High-k Bi-layer Control Technique

The impacts of interfacial layer (IFL) thickness and crystallinity of HfO
₂
/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSi
_x
/HfO
₂
) and pFETs (Ru/HfO
₂
) including BTI. It was found that crystallization of HfO
₂
causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO
₂
thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO
₂
/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500degC for the very first time.