A Novel P-Poly Gate PNOS Device Featuring High 2nd-Bit Operation Window for Multi-bit/cell Flash Memory Applications

A novel PNOS (P-poly Nitride-Oxide-Si) device that exploits gate edge assisted hole injection is proposed to reduce the 2
^nd
-bit effect. The device is erased by gate hole injection and programmed by the usual CHE (channel hot electron). Holes are injected from the gate edge using +FN and trapped in the SiN that produce local negative Vt along the channel edge. This edge device in turn causes enhanced DIBL that helps to provide a large 2
^nd
-bit window (> 4.5 V) that is suitable for MLC operation. Using this device, 4-bit/cell and 6-bit/cell operations are illustrated.