Performance Analysis and Design of Triple-Resonance Interstage Peaking for Wide-Band Cascaded CMOS Amplifiers

The analysis and design of the two promising candidates for interstage bandwidth enhancement of integrated wide-band cascaded amplifiers (CAs), namely series-shunt (SH) and shunt-series (HS) triple-resonance peaking, are presented. The principal operation of both peaking networks is described qualitatively in time-domain where the inherent bandwidth superiority of SH peaking is revealed. With the help of triple resonance concept, a rigorous and insightful analysis is then given in frequency domain. Analytical equations applicable to both networks have been derived to enable the proper inductance selection and to quantify the bandwidth advantage of SH peaking. In addition, various frequency characteristics of the networks are discussed through the investigation of their triple resonant frequency locations. This is followed by detailed analysis on the important nonidealities due to transistor's gate resistance and inductors' losses. The effectiveness of theoretical analysis is demonstrated via design and simulation of SHCA and HSCA with identical number of stages, gain and power consumption. The results show good agreement between theoretical analysis and simulation where the SHCA outperforms its HS counterpart in bandwidth while other performances are practically identical.