Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass

Today's digital systems design requires extensive system- level simulation to ensure that the right architectural trade-offs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the application. In order to run these simulations with adequate performance, design architects have increasingly employed abstract transaction-level models instead of RTL models to perform such analysis. Memory hierarchy is a major bottleneck for performance and energy consumption. Trying out every supported cache configuration to evaluate a given platform may become a very time consuming task. This paper proposes an approach for memory cache tuning, which is based on single-pass simulation. The proposed single-pass cache evaluation mechanism is 70 times faster than a simulation-based mechanism for the ADPCM application from Mediabench.