A Defect-Tolerant Architecture for Nanoelectronic Resistive Memories

We have calculated the useful density that may be achieved by the synergy of bad bit exclusion and advanced (BCH) error correcting codes in prospective hybrid (CMOS/nanodevice) resistive memories, as a function of the defective memory cell fraction. The results indicate that the memories with a CMOS/nano pitch ratio close to 3 (which is typical for the current, initial stage of hybrid circuit development), may overcome the usual resistive and flash memories with the same CMOS design rules in useful bit density if the fraction of bad nanodevices is below ~ 15%, even under rather tough (30 ns) restrictions on the total access time. Moreover, as the technology matures, and the pitch ratio approaches an order of magnitude, the hybrid resistive memories may be far superior to the densest semiconductor memories by providing, e. g., a 1 Tbit/cm
²
density even for a very conservative defect fraction of ~ 2%.