EEPROM Compact Model with SILC Simulation Capability

The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example is given and validated versus measurements.