New Results on Single-Step Power Control (SSPC) System in Finite State Markov Channel: Power Control Error Modelling and SSPC Modelling

The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate, and queueing variation is hard to access. In this work, we propose an approach to analyze that impact when being in finite state Markov channel (FSMC). To achieve the understanding of the relationship between SSPC, FSMC, and the queueing variation, power control error (PCE), error rate, and the PDF of queueing length are first calculated. PCE variation is modelled, which then benefits the evaluation of packet error rate (PER) and bit error rate (BER). Furthermore, based on these analysis, a SSPC model is proposed to simplify the overall system. The behavior of SSPC in FSMC can be better understood with the help of the proposed SSPC model. Simulation results have shown the validation of the proposed PCE variation model and SSPC model.