Technology Challenges for CMOS Density Scaling

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Continuous improvements in optical lithography have been a primary factor in enabling the economic benefits of geometric scaling. In fact, density scaling has long been synonymous with cost scaling. However, the complexity of sub-wavelength patterning has led to significant cost increases in scanners, pattern generation, mask & resist processing, and etching. In addition, since pattern fidelity depends on surrounding features in the immediate proximity, local variations have approached and now may exceed the level of global variations. These effects impose the use of additional statistical simulation to more accurately predict behavior across a die, and wafer, lot and fab, respectively. The cost, therefore, of improving density has reached far beyond the fab and is a major factor in the design of a product. We will examine the trade offs between continued density and performance scaling and cost improvements going forward, especially for 45/32nm CMOS low power products that integrate logic, memory and RF/analog for fully contained systems on a chip.