Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL

Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. Recently, a new language, SystemVerilog, was introduced and became an IEEE standard. SystemVerilog extends the hardware description language Verilog by including higher abstraction levels and integrated verification features. In this paper, we first present the concept of modeling multiple valued logic circuits in SystemVerilog. We demonstrate that this approach allows for efficient simulation of complex multiple valued logic systems. Secondly, we show how SystemVerilog can be used to ensure functional correctness. A generalization of binary toggle coverage for the multiple valued logic domain is presented and evaluated. As a test case, a scalable multiple valued logic arithmetic unit is modeled and experimental results for multiple valued logic toggle coverage are given.