Electroless Plating Ni-based Barrier Layers for Silicon Vertical Interconnects

A novel fabrication process for electroless plating NiMoP barrier layer on SiO
₂
was presented for 3D packaging with silicon vertical interconnects. The NiMoP film was deposited electrolessly by using a silane coupling agent as an adhesion and catalyzed layer. In addition, a potential NiMoP barrier/seed layer was successfully formed via electroless plating atop SiO
₂
after Pd activation. The composition and the electrical resistivity of NiMoP were investigated by scanning electron microscope (SEM) and four-point probe. The barrier layer and seed layer functions of NiMoP were verified by direct Cu electroplating and Auger electron microscope (AES)