3D Wafer Level Packaging Approach Towards Cost Effective Low Loss High Density 3D Stacking

As silicon semiconductor technologies continue to scale to smaller dimensions (vertical scaling), the realization of true systems-on-chip (SOC) devices with a large variety of functional blocks becomes very difficult to achieve. Technologies need specific optimization for logic, analog, memory etc. to reach the desired performance levels and circuit density. Furthermore, the substrates used to build active devices may vary significantly between technologies, including non-silicon substrates, e.g. compound semiconductors. Also systems may contain other planar components, such as MEMS and integrated passive devices. Besides the 'vertical' scaling there is also a 'horizontal' scaling. Realizing the full system on a single SOC die is becoming increasingly difficult and often not economically justified. If however a high-density 3D technology is available, a "3D-SOC" device could be manufactured, consisting of a stack of heterogeneous devices. This device would be smaller, lower power and higher performance than a monolithical SOC approach. A key feature for realizing true 3D interconnect schemes is the realization of vertical connections through the Si-die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as (i) a more traditional packaging approach, (ii) a wafer-level-packaging ('above' passivation) approach and (iii) a foundry level ('below' passivation) approach. The authors define these technologies as respectively 3D-system-in-a-package (3D-SIP), 3D-wafer-level-packaging (3D-WLP) and 3D-stacked-IC (3D-SIC) (Beyne, 2005). After a short overview on these three different types, this paper focuses on a 3D-WLP approach with innovative cost efficient through-Si vias for low loss high density 3D-stacking