Deep Sub-100 nm Design Challenges

This paper will describe the problems in the design and development of deep sub-100 nm system LSI's and/or SoC's. One of the most difficult problems is the large power consumption, in both active and stand-by modes. Another problem is how to improve the development efficiency of large scale chips and related softwares. Lithography, that has been getting harder and harder, directly impacts the chip yield. Several approaches to these problems will be discussed; various low power technologies from circuit to architecture levels, high-level language based design flow, IP reuse platform and DFM (Design for Manufacturing) related technologies.