An Area Efficient High Performance DCT Distributed Architecture for Video Compression

Discrete cosine transform (DCT), which is an important component of image and video compression, is adopted in various standardized coding schemes, such as JPEG, MPEGx and H.26x. But when compute a two-dimensional (2D) DCT, a large number of multiplications and additions are required in the direct approach. Multiplications, which are the most time-consuming operations in simple processor, can be completely avoided in the proposed architecture for real-time image compression. An area efficient high performance VLSI architecture for DCT based on the distributed arithmetic is proposed in this paper. Minimum number of additions is used to the DCT by exploiting the timing property of the DCT transform based on the distributed arithmetic. A case study of 8 times 8 DCT architecture based on the DA is analyzed. Savings exceeding 97% are achieved for the DCT implementation.