Low Power Trellis Decoder with Overscaled Supply Voltage

This paper is interested in applying voltage over-scaling (VOS) to reduce trellis decoder energy consumption, where the key issue is how to minimize the decoding performance degradation due to VOS-induced errors. Based on the fact that the integrity of different bits in the trellis state metric has (largely) different effect on the overall trellis decoding performance, we proposed an importance-aware clock skew scheduling technique that assigns those more important bits with longer timing slacks and hence better immunity to VOS-induced errors. This will provide system-level tolerance to VOS-induced errors in trellis decoders. With Viterbi and Max-Log-MAP decoders as test vehicles, we demonstrated that about 30% energy savings on trellis state metric computation can be realized with negligible decoding performance degradation