Notice of Violation of IEEE Publication Principles: A Fully-Integrated Single-Conversion SiGe BiCMOS Satellite LNB Front-End Using a Constant-Gain Full-Rate Oscillator

Notice of Violation of IEEE Publication Principles

"A Fully-Integrated Single-Conversion SiGe BiCMOS Satellite LNB Front-End Using a Constant-Gain Full-Rate Oscillator"
by Maxim, A.; Turinici, C.; Gheorghe, M.;
in the Proceedings of the 2007 IEEE Radio and Wireless Symposium,

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.
A fully-integrated satellite down-converter was realized in an advanced SiGe BiCMOS process that provides both 90 GHz f
_T
NPN HBTs used for the main signal path and 0.18μm CMOS FETs used for the frequency synthesizer reference clock path and calibration circuitry. A low phase-noise full-rate LC-VCO that covers both low and high L-bands was realized with an NPN differential amplifier and a MOS switched capacitor frequency calibration circuit. Offset-biased MOS accumulation varactors provide a virtually constant tuning gain by summing shifted C(V) curves that are uniformly distributed over the entire control voltage range. The loop filter was integrated on-chip by using a passive feed-forward architecture that provides a noiseless resistor multiplication. The LNB performance includes: <6 dB noise figure, 18 dBm output IP3, -106 dBc/Hz phase noise at 100 KHz offset, <0.4deg
_rms
integrated phase noise, 1.7x1.5 mm
²
area and 120 mA bias current from a 3.3 V supply