Increasing Throughput of Multiprocessor Systems

Many industrial applications require the use of multiple computing elements. The overall performance of such multiprocessor systems is a strong function of the communication capacity of the interconnection bus. By increasing this capacity one can integrate more processors, memory units, and input-output devices together and obtain a higher overall system throughput. In this paper, an analytic model is used to analyze alternative bus architectures. Both the local memory and global memory cases are analyzed; the instance in which the global memory case can be simplified is identified. Finally, the overall impact of implementing queues to increase computational throughput is analyzed.