CPU Model-Based Hardware/Software Co-design, Co-simulation and Analysis Technology for Real-Time Embedded Control Systems

This paper proposes a new development method for highly reliable real-time embedded control systems using a CPU model-based hardware/software co-simulation. We take an approach that allows the full simulation of the virtual mechanical control system including the mechatronics plant, microcontroller hardware and object code level software. This full virtual system simulation reveals the control system behavior, especially in microcontroller hardware and software. It enables microarchitecture design space exploration, control design validation, robustness evaluation of the system, software optimization before components design, and prevents potential problems. A novel aspect of this work is that the proposed virtual control system comprises all the components in a typical control system, therefore it enables the analysis of the effects from the different domains, for example the mechanical analysis of behavior due to a control software bug. To help the design, evaluation and analysis, we developed an integrated behavior analyzer into the development environment. This can display the processor behavior graphically during the simulation without affecting the simulation results, such as task level CPU load, interrupt statistics and software variable transition chart. This analyzer provides useful information on the behavior. No software modification is necessary for this virtual system analysis, and this analysis does not change the control timing and does not require any processing power on the target microcontroller. Therefore this method is suitable for real-time embedded control system design, in particular automotive control system design which requires high level reliability, robustness, quality and safety. In this paper, a Renesas SH-2A microcontroller model was developed on a CoMETtrade platform from VaST Systems Technology. An ETC (electronic throttle control) system is chosen as the plant to prove this concept. The ETB (electronic throttle body) model on Saberreg simulator from Synopsysreg was co-simulated with the SH-2A model. The SH-2A chip was under development during this project, nevertheless we could complete the OSEK OS development, control software design and verification using the virtual system. We confirmed that such software could run on an actual ETC hardware system without modification after a working sample chip was released at a later stage in the course of this work. This demonstrates that our models and simulation environment are sufficiently credible and trustful