High Data Reuse VLSI Architecture for H.264 Motion Estimation

Variable block size motion estimation in H.264 not only requires large computation complexity but also needs huge memory bandwidth. This paper proposes one high data reuse VLSI architecture for variable size motion estimation. The multi-bank memory organization reduces control complexity of reading and writing on-chip memory. The 16 4times4 sub-block sums of absolute differences (SADs) are combined from 256 primitive SADs by two levels cross network. Then other block size SADs can be obtained by reusing the 4times4 sub-block SADs. This architecture has been designed and synthesized in HJTC 0.18 um technology. The result shows it consists of 176 K gates and 41.6 KByte SRAM, operates at 55.6 MHz. The architecture allows the real-time processing of HDTV (1280times720) at 60 fps in a search range [-8, +7].