Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses

The power consumption and propagation delay are two important issues for global on-chip buses in deep submicron system-on-chip design. And inter-wire coupling is a major source of the two issues. In this paper, we present a new bus encoding scheme for generic on-chip data buses that simultaneously reduces coupling power consumption and eliminates capacitive crosstalk. Experimental results indicate that our proposed scheme can provide about 21% bus power reduction on average while minimizing the crosstalk delay. Furthermore, we employ a bus-invert coding technique to improve the power efficiency of the proposed approach by up to 7.7%