Standard CMOS voltage multipliers architectures for UHF RFID applications : study and implementation

An analysis of RFID multipliers architectures is presented. An analytic model of classical Mosfet multiplier is given, which permits to determine the main design parameters of this kind of circuit and their impacts on efficiency. Thanks to this study a new architecture is proposed in order to increase efficiency. The two multipliers are designed and implemented in the same standard 0.18
mu
m CMOS process. Measurements have been done and show functionality of the multipliers and improvement between the architectures.