Access Queues for Multi-Bank Register Files Enabling Enhanced Performance of Highly Parallel Processors

The proposed register access queues are used as part of a scheduler which avoids possible access conflicts for a multi-bank register file in the highly parallelized processor. From the design and implementation in 180 nm CMOS technology, a multi-bank register file with the access queue realizes 65 % smaller area and 64 % higher clock frequency when compared with a conventional multi-port-cell register file. Since the cycle-based execution performance of the processor remains practically unchanged, the higher clock frequency translates directly into higher processor performance