An Efficient Parallel Architecture for Matrix Computations

This paper introduces a new versatile and high-performance parallel hardware engine for matrix computations based on distributed memory. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies. The core computes matrix power, multiplication, and inversion. The matrix power presented in this paper is mathematically proven to be two times faster than normal computations, scalable and just needs two input elements of the input matrix per each clock cycle. As well, the design is optimized to suitably perform least square computations in signal processing applications. The synthesis results on FPGA platforms indicate that the proposed architecture can operate in 75 MHz for 16 bit word length and the peak attained performance is about 2400 MMAC operations with 32 concurrent MAC modules