A Low-Power Phase-Locked Loop for UWB Applications

This paper describes a low-power phase-locked loop (PLL) design for multiband-OFDM UWB synthesizer implemented in a 0.13-mum CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of -54 dBc and in-band phase noise of -78 dBc/Hz