An Efficient Iterative Synchronization Scheme for LDPC-Coded DS-SS Systems Using two Samples per Chip

In this paper, an efficient iterative timing and carrier phase recovery scheme is proposed for LDPC-coded direct sequence spread spectrum (DS-SS) systems. The received signal after the chip-matched filter is two times over sampled per chip. The characteristics of DS-SS signal and LDPC decoder are explored to make the synchronization scheme efficient and simple in such a low sampling ratio. Three sets of correlation values provided by three correlators with different timing offsets are stored to estimate timing and carrier phase. The estimation is performed once per decoding iteration based on the maximum likelihood theory aided by hard decision obtained from LDPC decoder. The overall complexity of this scheme is very low and the performance of the proposed scheme approaches that with the ideal synchronization on AWGN channels