Register File Partitioning with Constraint Programming

Highly parallel processors call for high bandwidth register access. One solution is to use multi-port register files. However, such register files are expensive in terms of chip area and their access time can lower the maximum clock frequency of the processor. Therefore, partitioning the multi-port register file to several smaller register files with less ports is preferred. In this paper, the partitioning of the register file is studied and the problem is formalized into such a form that constraint programming paradigm can be used to search for applicable register file partitionings. With the aid of the proposed method, applicable register file partitions with no performance penalty can be found and the inherent drawbacks of multi-port register file can be avoided