Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources

In this paper we address the synthesis of digital signal processing cores, aiming at FPGAs with heterogeneous resources. A novel synthesis procedure able to distribute the usage of logic-based and embedded resources is presented. A multiple word-length approach is taken since it has proven to provide significant area saving when compared to the traditional uniform word-length approach. We analyze two key factors regarding previous multiple word-length DSP synthesis approaches: (i) the impact of extending the size of the logic-based resource set; and (ii) the impact of combining both logic-based and embedded resources. The proposed synthesis method efficiently combines logic-based and embedded resources achieving area improvements of up to 66% when compared to previous approaches