Evolutionary Synthesis of Synchronous Finite State Machines

Synchronous finite state machines are very important for digital sequential designs. They allow the synchronisation of the hardware system components so that these may cooperate adequately in the fulfilment of the main objective of the design. In this paper, assuming that the state assignment problem has been solved and so a specific state coding is provided, we propose to use the evolutionary methodology to yield optimal evolvable hardware that implements the state machine control component. The evolved hardware requires a minimal hardware area and introduces a minimal propagation delay of the machine output signals.