An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design

Capacitive coupling is the primary source of noise in nanometer technology digital CMOS VLSI circuits. It becomes worse with technology scaling. The interconnect capacitive crosstalk noise can be characterized by two parameters: peak noise voltage, and delay uncertainty. Delay uncertainty optimization can be seen as a subset of interconnect delay optimization. This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that cross-capacitances are optimally shared for simultaneous noise and delay minimization. Using an Elmore delay model including cross capacitances for a bundle of wires and well-known crosstalk models, we show that "symmetric hill" wire ordering according to the strength of signal drivers, which is known to optimize channel timing characteristics, can be used also for minimizing channel noise metrics. Examples using state-of-the-art circuits in 65-nanometer technology are analyzed and discussed.