Power-Supply Noise Attributed Timing Jitter in Nonoverlapping Clock Generation Circuits

This paper describes an analysis of timing jitter induced by power-supply noise in nonoverlapping clock generation circuits typically used in switched-capacitor sigma-delta modulators. Substrate noise effects are also included but not treated as a separate phenomenon since the MOSFET bulk contacts are connected to the power-supply or ground. Two different nonoverlapping clock generation circuits have been compared and treated independently: the NOR based and the NAND based architectures. Furthermore, all possible connection topologies of the circuit blocks in the clock generation circuits are investigated. Monte Carlo simulations have been performed in Spectre at BSIM3v3 transistor model level using parameters from a 0.18mum process to show which of the topologies is most suitable as clock generator for wideband applications. In terms of timing jitter sensitivity to power-supply noise, the NOR based architecture is slightly more robust and suitable for providing a timing reference to a sampling circuit