Circuit Optimization Using Scale Based Sensitivities

Most robust circuit sizing and optimization algorithms require detailed information about the sensitivity of circuit performance to device behavior. Additionally, rapid technology scaling and the introduction of novel device structures to extend CMOS scaling is resulting in the rapid introduction of new models into our simulation infrastructure. In this paper we present a novel technique for the efficient computation of circuit performance sensitivity in a model independent manner. The advantage of our method is that it allows rapid deployment of accurate optimization methods even for new or exploratory models. We demontrate the use of these gradients in circuit optimization to generate an area vs. timing variability trade-off curve for an SRAM cell design in the presence of N and P device threshold voltage variations.