Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture

This paper presents a method of on-chip communication bus topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We define the problem of on-chip communication topology synthesis into two main problems namely scheduling and allocation binding problem. The communication behavior of each module is modeled as a set of communication lifetime intervals (CLTIs), which are evaluated and scheduled for different size of bus width to get the minimum number of overlaps, minimum size of bus width and the minimum number of bus(es) using tabu search method. These optimized CLTIs are given to the clique partitioning algorithm as an allocation-binding problem to synthesize the communication topology