Design of a high speed interface for 0.5/spl mu/m gate arrays

Modern systems running at clock rates of 50-150 MHz need high-performance interfaces for use between different logic and memory chips on the PCB. There is also a need for very tight clock skew control. The author examines the requirements of high-performance input/output buffers (I/Os) and clock skew control for 0.5-/spl mu/m gate arrays. In order to produce a cost-effective and performance-optimized I/O, it is sometimes necessary to use embedded I/O constructions. These are where the I/O structures are customized for a given application from a series of predesigned options.<
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