An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures

Circuit-switched networks provide guaranteed transmission latency and throughput, and hence are suitable for many network-on-chip (NoC) architectures requiring quality-of-service. A circuit-switched on-chip network needs a scheduler to arrange communication paths and allocate a proper bandwidth for each path. Such a scheduler offers an effective solution for a critical step in the NoC design. In this paper, we propose an efficient scheduler for pre-scheduled circuit-switched on-chip networks. Based on simulations, we show that low delivery latency for circuit-switched on-chip networks can be achieved with our scheduler. Furthermore, with efficient scheduling, the cost of the switches can be also minimized