Digital transistor sizing techniques applied to 100K ECL CMOS output buffers

Regulated current levels have been maintained with a control circuit that digitally adjusts the effective width of a 0.9-/spl mu/m CMOS output buffer to generate 100 K ECL levels operating up to 800 MHz. A pseudo-random bit error rate test of the buffer operating at 1.6 Gb/s indicated no errors Digital sizing reduces the variation of internal power dissipation over operating conditions from 250% to 10%.<
>