ECL I/O buffers for BiCMOS integrated systems: A tutorial overview

The authors describe the methodology for the design and layout of fast BiCMOS ECL I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature and supply voltage compensated and have nominal rise and fall times of 400 ps.<
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