Parallel VLSI Implementation of the Kalrman Filter

The problem of parallel implementation of the square-root Kalman filters is addressed. At the system level, our approach is to apply systolic-type VLSI processor arrays as basic building blocks to accelerate the matrix operations required in each iteration. To maximize the parallelism, we also exploit an inter-array pipelining scheme through the overlapping of execution between successive processor arrays. We estimate that with (5n2 + r2 + 8nr + n + 3r)/2 processors, it would take max[(4n + 2r, 2n + 4r-2)] time units to complete one Kalman filter iteration, where n is the dimension of the underlying state space model and r is the dimension of the input vector.