A CMOS circuit technique for high-speed RAMs

Recently, CMOS circuits at clock speeds normally described with ECL have been demonstrated. The author presents a technique for including RAM structures in such designs. Pipelining the address decoder and integrating a fast sense amplifier in the high-speed CMOS technique allows integration of small RAMs in circuits running at several hundred MHz. A 420 MHz, 32 word by 64-b register file has been designed in 1/spl mu/m CMOS.<
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