JOGM: A CMOS cell layout style using jogged transistor gates

A new width minimizing layout style called jogged gate matrix (JOGM) for CMOS cells is described. The traditional gate matrix layout style is modified by inserting 45/spl deg/ jogs into transistor gates. Thus, JOGM improves CMOS cell width by 23% to 31% in comparison to traditional gate matrix layout. An approach for automatic layout generation is suggested.<
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