Evaluation and Design of Processor-Like Reconfigurable Architectures

Traditionally, FPGAs are deployed because of their flexibility to change the application over time. Newly developed architectures can be reconfigured within one clock cycle so that components of a device can be re-used within a single application. The reconfiguration keeping pace with the execution yields an additional degree of freedom that constitutes a new principle of reconfiguration. This principle is called processor-like reconfiguration. In the presented work, it is evaluated how processor-like reconfiguration can be exploited by a high-level compiler and which architectural resources are needed for an efficient mapping of applications. For an assessment of the benefits and costs imposed by those resources, a synthesizable model for coarse-grained reconfigurable architectures is used.