Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study

In this paper we present a 3D simulation study of the effect of Fermi level pinning along polysilicon gate grain boundaries on nano-MOSFET variability. Pinning of the Fermi level results in variations between devices depending on the random pattern of grain boundaries within the gate. We present a coherent 3D simulation methodology demonstrating the necessity of statistical simulations. As an illustration of our approach, we have carried out a statistical analysis of the variation in threshold voltage induced by polysilicon grain boundaries for a 30 nm MOSFET