Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs

In this work we investigate the performance of fully-depleted silicon-on-insulator (SOI), double-gate (DG) and cylindrical nanowire (CNW) FETs, with the aim of establishing optimization procedures and appropriate scaling rules towards their extreme miniaturization limits. The simulation model fully accounts for quantum electrostatics; current transport is modeled by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements. The simple rule resulting from this investigation is that stringent short-channel effect constraints can be fulfilled at a constant oxide thickness of 2 nm, with L
_g
/t
_Si
ap 5 for the SOI-FET, L
_g
/t
_Si
ap 2 for the DG-FET, and L
_g
/t
_Si
ap 1 for the CNW-FET