CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

We report a novel dual metal gate (MG) integration technique for gate-first CMOS process by intermixing (InM) of ultra-thin metal and metal nitride (MNx) films at high temperature together with source/drain (S/D) activation process. In this process, a thin (~2 nm) TaN buffer layer is used to prevent the gate dielectric being exposed during the metal etching process. Work function (WF) of TaN can be adjusted for NMOS/PMOS by intermixing of the TaN buffer layer with other metals on top of TaN during S/D activation. Prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) have been integrated on a single wafer, with WF of 4.15 eV and 4.72 eV achieved, respectively. Successful Vth adjustment and good transistor characteristics are also demonstrated on HfTaON dielectric.