Efficient Optimization Methodology in Early-Stage Design of Mesh-structured On-Chip Power/Ground (P/G) Networks

Due to decreasing supply voltages and increasing power consumption of today's VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during floorplanning stage in the today's physical design flow. It is therefore very important to adjust the double-mesh P/G grids in the floorplanning for efficiently minimizing the worst-case IR drop subject to limited routing resource in early-stage P/G network design of high-end chips. In this paper, the author presented a novel feasible methodology to efficiently optimize the problem of mesh-structured center-bumped P/G grids under given routing resources. In Zhang, L-H and Luo, Z-Y, 2004, they have proposed the approximate current distribution (ACD) simulation method and the OS_SMACD optimization approach for early-stage single-level P/G meshes. In this work, a feasible theory is induced to directly compute the optimal solutions OS_DMACD for practical double-mesh P/G grids of high-end chips. Experimental results show that OS_DMACD matches very well with the exact counterparts inefficiently obtained with ICCG, which can leads to significant speedup in the today IR-drop aware floorplanning